1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method.
2. Description of the Related Art
With high integration and high functionality of semiconductor devices, semiconductor patterns have been made finer and finer year after year. High integration has been particularly advancing in memory devices, so that still finer semiconductor patterns are required to be formed for gate electrodes or metal wires in the memory devices.
Semiconductor patterns are generally formed by exposure technique. The resolution of the exposure depends on the minimum dimension of the pattern and the pitch of the pattern. To realize the fine patterns, continuous technological innovation is being made in the exposure technique. However, there is a limit on how far the resolution of the exposure can be made fine. Such a limit arises from the wavelength of light and an electron beam used in the exposure. In principle, it is almost impossible to further reduce the resolution achievable in the exposure technique.
At the same time, recently, there has been an increasing demand to lower the resolution of the exposure than its current lower limit. Accordingly, as a conventional technique to respond to such a demand, in JP-A 2002-280388 (KOKAI), for example, there is proposed a method for forming a line-and-space pattern having a pitch finer than the lower limit of the resolution achievable in the exposure technique.
However, according to the conventional technique, while an ultra fine pattern exceeding the lower limit of the resolution achievable in the exposure is considered, the formation of a wider pattern at the same time is not considered.